PURPOSE: To increase the processing speed by dividing input data indicating a binary number into groups each of which consists of plural bits and providing logical operation processing parts and carry signal transmission control parts for respective groups.

CONSTITUTION: Input data A1 to A16 and B1 to B16 are divided to groups each of which consists of plural bits, and logical operation processing parts 1A1 to 1A8 and carry signal transmission parts 2A1 to 2A8 are provided correspondingly to respective groups, and transmission of a carry signal inputted from the preceding stage to the succeeding stage is controlled in accordance with logical operation processing results of plural corresponding bits in respective groups. Consequently, the number of transistors required for transmission of the carry signal is reduced. Thus, the transmission time of the carry signal is shortened to increase the processing speed as the whole of a circuit.