PURPOSE: To enable suppression of an increase in the chip area of a logic gate and in the number of MOS transistors Tr and terminals thereof by connecting a resistance element to a Tr network of one conductivity type and a Tr to a Tr network of the other conductivity type, in parallel respectively.

CONSTITUTION: Between a supply power source VDD and an output terminal 51 of a logic gate, a resistor 13 is connected in parallel to a P-channel MOS transistor (P-MOS Tr) network 11, and between the terminal 51 and a grounding potential, N-MOS Tr 14 is connected in parallel to an N-MOS Tr network 12. Then, a stack open fault test mode (STOM) of the Tr network 11, for instance, out of the Tr networks 11 and 12 and an ordinary mode thereof are unified, and this unified mode and the SOTM of the other Tr network 12 are joined together, whereby the modes as a whole are reduced to two. According to this constitution, transistors, input terminals of control signals, etc. included in the logic gate can be reduced, an increase in the chip area of the logic gate and the number of terminals thereof is suppressed, and besides, a delay time in operation can be shortened by the reduction in the number of transistors.