PURPOSE: To prevent the titled logic integrated circuit from being entered to a test mode by mistake during normal operation without increasing the number of terminals of the integrated circuit by accessing a test mode setting register with a logical pattern which has no possibility in the normal operation.

CONSTITUTION: The signal on the clock input signal 10 of a D flip-flop 9 is generated by gates 6 and 7 and an address decoder 8. At this time, the clock input on the line 10 is not generated because of a gate 6 unless a read pulse on a read pulse signal 2 and a write pulse on a write pulse line 3 are generated at the same time. When the read pulse and write pulse are generated at the same time and the test mode is entered, a test circuit is so constituted that the output of a multistage counter 102 is led out from a terminal 104 through a mode switching means 100 after being passed through a multistage counter 103, thereby decreasing the number of clocks inputted to a terminal 101 at the time of a check on the connection between the terminals 101 and 104.