PURPOSE: To enable mixed simulation with other logic circuits which are described at a resistor transfer level without lowering an HW flowchart, which is generated at the time of high-order design, to a description of the resistor transfer level when the logic of a logic verified.

CONSTITUTION: A conditional FANOUT information generating means 1 judges the operation conditions of the FANOUT operation of respective symbols and respective constituent elements as to logic circuit information A represented with the HW flowchart and logic circuit information B represented at the resistor transfer level. Further, a logical operation information generating means 2 analyzes the logical operation of the respective symbols and respective constituent elements. Lastly, a simulation means 3 performs arithmetic according to the logical operation of the respective symbols and respective constituent elements to perform the simulation while judging the FANOUT conditions.