To suppress a gate capacity load connected to a clock node to the same capacity with a single-FF circuit and to reduce the power consumption of part of a clock tree by controlling the output state of held data according to the result of a coincidence comparison between the current logical value of input data and a logicals value before it.

The result of the coincidence comparison between an input value to a double-FF circuit and the held logical value of the latch 22 of a slave part 20 is used as a signal for placing the transfer gate 13 of an output stage of a latch 12 of a master part 10 in a 'transmission state', and the result of a coincidence comparison between the input value to the double-FF circuit and the held logical value of the latch 22 of the master part 10 is used as a signal for placing a transfer gate 23 of the output stage of the latch 22 of the slave part 20 in a 'transmission state'. Consequently, data are latched with both leading and trailing edges of a clock and the gate capacity load connected to the clock node an be suppressed to the same capacity with the single-FF circuit.