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Title:
LOGIC TESTER
Document Type and Number:
Japanese Patent JPS5527907
Kind Code:
A
Abstract:

PURPOSE: To check intermittent abnormalities quickly by making multiple sampling in one cycle of decision results of tested logical signals.

CONSTITUTION: A tested logic circuit 12 transfers determined output from a tester control circuit 15 to a check circuit 13 in response to a special pattern. In the circuit 13 a comparison circuit 31 compares tested signals with a threshold value by the level, supplies test signals to a decision circuit 32. The coincidence of the logical level with an expected value pattern is decided and the decision outputs are written in a fail memory 33 one after another by use of a multiple sampling clock.


Inventors:
NAKAO TOSHIYUKI
Application Number:
JP10006278A
Publication Date:
February 28, 1980
Filing Date:
August 18, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G01R31/28; G01R29/02; (IPC1-7): G01R31/28



 
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