LOGICAL CHIP

Japanese Patent JPH08204162

A

PROBLEM TO BE SOLVED: To realize high use, high level of integration, and high performance of a chip surface, by mixedly forming standard cell logic circuits and gate array cell logic circuits in the manner in which at least a part of the standard cell logic circuits are arranged to be adjacent to the gate array cell logic circuits. SOLUTION: Logic circuits such as NAND's, inverters and latches are formed at the internal cell location 12 of a standard cell chip 10, and I/O circuits are formed at the external cell location 14. A guard ring 16 which evades the problem of latchup concerning CMOS circuits and makes it minimum is formed around the chip. The chip main body consists of P-type silicon, and the guard rig 16 contains N-type impurities. The letter S at the cell positions 12, 14 indicates the standard cell formed in the regions. The letter U indicates the cell location which is not used. Each of the internal cells 12 is demarcated by lines 18, and the external cells 14 are demarcated by lines 20. Thereby hardware is easily changed without deteriorating the integration density of a chip surface and the performance of a device.

ERIOTSUTO ROORENSU GOURUDO
DAGURASU UEIN KEMERAA
RANSU ARAN MAKUARISUTAA
RONARUDO ARAN PAIRO
GAI REIMONDO RICHIYAADOSON
DEBORA AN UERUBAAN

JP20293995A

August 09, 1996

August 09, 1995

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IBM

H01L21/82; H01L21/822; H01L27/02; H01L27/04; H01L27/118; (IPC1-7): H01L27/118; H01L21/82; H01L27/04; H01L21/822

JPS61202450A	1986-09-08
JPS60234231A	1985-11-20
JPS6124250A	1986-02-01
JPS60234341A	1985-11-21
JPS60110137A	1985-06-15
JPS61123153A	1986-06-11

Kiyoshi Goda (2 outside)

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