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Patent Searching and Data


Title:
LOGICAL CIRCUIT SIMULATOR FORMING SYSTEM
Document Type and Number:
Japanese Patent JPH04115330
Kind Code:
A
Abstract:

PURPOSE: To make this logical circuit simulator forming system appropriate for a large scale circuit by newly forming a simulator inputting only an evaluation routine necessary for the simulation of a circuit to be simulated at the time of determining the circuit.

CONSTITUTION: A circuit constituting element evaluating routine is formed as an evaluation routine source file (a) and compiled in an object file (b) by a compiling means 1. Since the formation of plural files (b) corresponding to the number of sorts of the circuit constitution elements to be used for circuit design is necessary, the plural files (b) is combined as a file (c) by a library forming means 2. At the time of determining an objective circuit, an evaluation routine name list (e) is formed by an evaluation routine name extracting means 3 based upon circuit data (d). A linking means 4 extracts only the evaluation routine included in the list (e) from the file (c) based upon the list (e) and forms a new simulator g1 linked with a center file (f).


Inventors:
ASAO KIYOSHI
Application Number:
JP23657390A
Publication Date:
April 16, 1992
Filing Date:
September 06, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F9/06; G06F11/26; G06F17/50; (IPC1-7): G06F9/06; G06F11/26
Attorney, Agent or Firm:
Shin Uchihara