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Title:
LOGICAL CIRCUIT USING GATE JUNCTION TYPE FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS5762632
Kind Code:
A
Abstract:

PURPOSE: To make a logical circuit high-density, by using a normally off-type junction gate field effect transistor as a load of a normally off-type junction gate field effect transistor for logic and by providing a junction diode between the gate and the source of the transistor as a load.

CONSTITUTION: N channel normally off-type GaAsMESFETs 10 and 40 for logical operation and load which constitute an NOT circuit are cascaded, and a GaAs Schottky junction diode 50 is connected in the same rectifying direction as gate and source electrodes of the MESFET for load. When a voltage Vl between the drain and the source of the load is minute, the channel is closed by a gate depletion layer and a load current Il is not flowed; but when the voltage Vl is increased, the current Il starts flowing; and when the voltage Vl is increased furthermore, the gate electrode becomes high, but the gate potential becomes a voltage higher by the forward voltage (Vfd) of the diode due to action of the diode 50, and the MESFET for load is biased fixedly to Vfd, and the Il shows a saturation characteristic. This load characteristic is changed optionally by the ratio of gate width of MESFETs.


Inventors:
KOZUKA MICHI
Application Number:
JP13803080A
Publication Date:
April 15, 1982
Filing Date:
October 02, 1980
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K19/0952; (IPC1-7): H03K19/094



 
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