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Patent Searching and Data


Title:
LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JPS6048616
Kind Code:
A
Abstract:

PURPOSE: To decrease the signal propagation time and also to reduce the occupied area in constituting an integrated circuit by connecting the 1st input terminal to a gate of the 2nd P and N-channel MOS transistors (TRs).

CONSTITUTION: Since the input terminal 1 is connected only to the gate of the P-channel MOS TR10 having a high impedance and the gate of the N-channel MOS TR12, the input capacitance is very small and the signal propagation time is decreased. Further, the circuit consists of five P-channel MOS TRs and five N-channel MOS TRs and the area of a mask pattern is decreased in constituting an integrated circuit.


Inventors:
KIKUCHI KOUICHI
NAGAKUBO SHIGEAKI
Application Number:
JP15645483A
Publication Date:
March 16, 1985
Filing Date:
August 29, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
NIPPON ELECTRIC ENG
International Classes:
H03K19/0175; H03K19/017; H03K19/094; H03K19/0948; (IPC1-7): H03K19/00
Attorney, Agent or Firm:
Sumita Toshimune