Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
LOGICAL SIMULATOR
Document Type and Number:
Japanese Patent JPH0383169
Kind Code:
A
Abstract:

PURPOSE: To obtain a simulation result wherein time deviation is considered by setting a potential level, where the time zone between the input/output mode switching time and tester input/output mode switching time of a two-way input/ output terminal in the same cycle is obtained from the two-way input/output terminal, in an unsteady state.

CONSTITUTION: An input/output mode switching decision means 31 fetches an internal signal SIM result 4 and detects the input/output mode of the input/ output terminal of an integration circuit to outputs an input/output mode switching decision result S31 to a simulation execution control means 33. When an input/output mode switching time detection signal is inputted, the simulation execution means 33 sets the potential level, obtained from the two-way input/ output terminal, in the unsteady state in the time zone between the input/output mode switching time and tester input/output mode switching time of the two-way input/output terminal in the same cycle. Therefore, the simulation result wherein the time difference between the input/output mode switching time and tester switching time in the same cycle is considered can be obtained. Consequently, the same simulation result with that when the operation of the integrated circuit is tested by a tester is obtained.


Inventors:
NISHITANI KAZUHARU
Application Number:
JP22089289A
Publication Date:
April 09, 1991
Filing Date:
August 28, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/25; G06F11/26; G06F17/50; G01R31/28; (IPC1-7): G01R31/28; G06F11/26; G06F15/60
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)