Title:
LOW-STRAIN UNIT-GAIN AMPLIFIER FOR DIGITAL TO ANALOG CONVERTER
Document Type and Number:
Japanese Patent JPH05102740
Kind Code:
A
Abstract:
PURPOSE: To provide a unit gain buffer circuit for a digital-analog converter(DAC) using a switched capacitor filter. CONSTITUTION: The sources of differential input transistors 190 and 200 are connected to a common node 202. A current source transistor 214 is connected between the node 202 and an earth to supply a current source. Constant current sources by transistors 222 and 230 are connected to each drain of the differential input transistors. Cascade devices 216 and 226 are connected to the drains of the transistors 190 and 200 to keep a drain-source voltage in constant when an input common mode signal is large. The fluctuation of the bias of the transistor 214 is absorbed by feedback transistors 232 and 234 which form a variable current source to the node 202. These transistors are controlled by the voltage of the drains of the transistors 190 and 200.
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Inventors:
JIEFURII UIRIAMU SUKOTSUTO
Application Number:
JP2577792A
Publication Date:
April 23, 1993
Filing Date:
January 16, 1992
Export Citation:
Assignee:
CRYSTAL SEMICONDUCTOR CORP
International Classes:
H03F1/32; H03F3/30; H03F3/343; H03F3/45; H03H19/00; H03M1/08; H03M1/66; H03M3/02; (IPC1-7): H03F1/32; H03F3/343; H03H19/00; H03M1/08; H03M1/66; H03M3/02
Domestic Patent References:
| JPS62176313A | 1987-08-03 | |||
| JPS63185208A | 1988-07-30 | |||
| JPS63117503A | 1988-05-21 |
Attorney, Agent or Firm:
Koichiro Kato (2 outside)