Title:
LOW-VOLTAGE DIFFERENTIAL CIRCUIT
Document Type and Number:
Japanese Patent JPH06120810
Kind Code:
A
Abstract:
PURPOSE: To operate a circuit used for a logic cell or a multiplier at a low voltage by using a plurality of operating transistors(TRs) pair. CONSTITUTION: A logic cell is provided with an input differential pair, consisting of NPN TRs Q1 , Q2 and an output differential pair consisting of NPN TRs Q3 , Q4 . Output terminals of the output differential pair Q3 , Q4 are coupled with output terminals of the cell by a couple of emitter follower TRs Q7 , Q8 . A switching circuit has a differential pair, consisting of PNP TRs Q9 , Q10 connecting to a common current source Ix1 . When a clock phase is set to a 1st phase, the input differential pair Q1 , Q2 are active and respond to a data input. The output differential pair Q3 , Q4 are active in a 2nd phase of the clock phase and data stored in the input pair are transferred to the output pair, consisting of the TRs Q3 , Q4 , and transferred to the output terminals of the cell by the TRs Q7 , Q8 .
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Inventors:
MAAKU DEI MAKUDONARUDO
Application Number:
JP15737993A
Publication Date:
April 28, 1994
Filing Date:
June 28, 1993
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP
International Classes:
G06G7/163; H03D7/12; H03K3/2885; H03K19/086; (IPC1-7): H03K19/086; G06G7/163; H03D7/12
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)
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