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Title:
LSI PACKAGE
Document Type and Number:
Japanese Patent JPS60178649
Kind Code:
A
Abstract:

PURPOSE: To contrive the improvement in holding factor for outer circuit connection signal terminals by reducing the ground resistance and power source circuit resistance by a method wherein a substrate for LSI chip loading is provided with two electrode patterns for ground and power source, and a cap for LSI chip protection is provided with outer circuit connection terminals for the ground and power source electrodes.

CONSTITUTION: The substrate 1 for LSI chip loading is provided in the outer periphery of a bonding pad 3 with the first electrode pattern 6 of frame form exposed to the surface that short-circuits a plurality of bonding pads 3-1 connected to the ground (or power source) electrode of the LSI chip, and in the outer periphery of this pattern 6 with the second electrode pattern 7 of frame form that short-circuits a plurality of bonding pads 3-2 connected to the power source (or ground) electrode of the LSI chip. The connection of the bonding pads 3-2 to the second electrode pattern 7 is made by means of a through hole 8 through the inner layer of the substrate, so that the first electrode pattern 6 is not electrically short-circuited with the second electrode pattern 7.


Inventors:
KADOMA YASUYUKI
Application Number:
JP3481184A
Publication Date:
September 12, 1985
Filing Date:
February 25, 1984
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L23/12; H01L23/06; H01L23/498; H01L23/50; (IPC1-7): H01L23/06; H01L23/12; H01L23/48
Attorney, Agent or Firm:
Kurita Haruo



 
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