PURPOSE: To speed up a sense processing for LSI to be controlled.

CONSTITUTION: At the time of sensing, sense designation information and address (LSI input data) are transmitted from a controller 2 to an LSI1 to be controlled while synchronized with a clock. Then, the clock is stopped and the data is latched by a data latch register 3. When a transmission end signal is sent in this state, a latch enable signal is generated by a timing generation part 5 and sent to a PUS conversion register 6. The P/S conversion register 6 takes out the data of the specified address from a monitoring control register 4A to be latched(parallel data). After that, when the supply of a clock is started, the data in the latched P/S conversion register 6 is transmitted to the controller as sense data.