MAGNETIC RANDOM ACCESS MEMORY WHOSE PARASITIC CURRENT IS REDUCED

Title:

MAGNETIC RANDOM ACCESS MEMORY WHOSE PARASITIC CURRENT IS REDUCED

Document Type and Number:

Japanese Patent JP2004006861

Kind Code:

A

Abstract:

To reduce power consumption and level of parasitic current of a magnetic RAM device.

The data storing system includes the magnetic random access memory (MRAM) device (500) having several memory cells (102). Each of the memory cells (102) includes a magnetic tunnel junction (MTJ) (202) and a non-magnetic tunnel junction (NMTJ) (204) which are connected in series. The magnetic tunnel junction (202) stores a bit value corresponding to a logical value high (1, for example) or a logical value low (0, for example). The non-magnetic tunnel junction (204) provides a low resistance when the memory cells (102) are read out and provides a considerably high resistance when the memory cells (102) are not read out. Consequently, the level of the parasitic current which is leaked through the memory cells (102) which are not read out is negligible.

Inventors:

KENNETH K SMITH
VANBROCKLIN ANDREW
FRICKE PETER J

Application Number:

JP2003129164A

Publication Date:

January 08, 2004

Filing Date:

May 07, 2003

Export Citation:

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Assignee:

HEWLETT PACKARD DEVELOPMENT CO

International Classes:

G11C11/15; G11C11/16; H01L21/8246; H01L27/105; H01L43/08; (IPC1-7): H01L27/105; G11C11/15; H01L43/08

Attorney, Agent or Firm:

Satoshi Furuya
Takahiko Mizobe
Kiyoharu Nishiyama

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