PURPOSE: To accelerate following access request processings concerning the main memory data write control method to be executed when a store instruction is issued.
CONSTITUTION: A central processing unit(CPU) 1 retrieves whether the data of a write object are stored in a cache 22a according to a preceding pipelined processing or not, the write request of write data is issued to a main storage device 3 according to a following pipelined processing and when it is judged that the data of the write object are held, the write data are written in the cache 22a in this main memory data write control method. When it is judged that the data of the write object are held in the cache 22a according to the preceding pipelined processing, the access request to the following cache 22a is inhibited and processed so as to start the execution of the following pipelined processing. On the other hand, when it is judged that the data are not held, while permitting the following access request, it is processed to start the execution of the following pipelined processing.
JPH0348932 | MEMORY ACCESS CONTROL METHOD |
JPS59218555 | MICROPROGRAM CONTROL DEVICE |
OSONE HIDEKI
JPH01318119A | 1989-12-22 | |||
JPS61165136A | 1986-07-25 | |||
JPS59213084A | 1984-12-01 |