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Patent Searching and Data


Title:
MALFUNCTION PREVENTING SYSTEM IN CLOCK SELECTION
Document Type and Number:
Japanese Patent JPH01289332
Kind Code:
A
Abstract:

PURPOSE: To prevent malfunction and to attain efficient system test by detecting the disturbance in the duty ratio and the alternate code rule of an input pulse of a high speed clock and interrupting the transmission of an output frame clock from a detector by a mask in the detection of any disturbance thereby preventing the clock from being outputted to a PLO/DIS section.

CONSTITUTION: Pulse missing detectors 11N, 11E check the presence of missing pulses of a prescribed number or over as to high speed clocks 64KN, 64KE of the systems N, E to be inputted. A disturbance detection circuit 12 select the high speed clocks 64KN, 64KE of the systems N, E to be inputted by using outputs Cn, Ce of the detectors 11N, 11E thereby detecting the disturbance in the duty ratio of the high speed clock pulses and in the prescribed code rule. Then a detection signal ALM of a disturbance detection circuit 12 is given to a mask circuit 13 to apply gate processing to an output 8Ko of a frame detector 17 and the input clock 8Ko synchronously with a high speed clock without any disturbance in the high speed clocks 64KN, 64KE of the systems N, E to be inputted is outputted as a reference output. Thus, malfunction due to noise caused at the changeover of the inputted two system clocks is prevented.


Inventors:
TAKAHASHI YUJI
KAMOI NOBUHISA
YOSHINO TOYOHIKO
Application Number:
JP1988000119864
Publication Date:
November 21, 1989
Filing Date:
May 17, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04J3/06; G06F1/04; H04L7/00; (IPC1-7): G06F1/04; H04J3/06; H04L7/00