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Patent Searching and Data


Title:
MALFUNCTION PREVENTION ARBITRATION SYSTEM
Document Type and Number:
Japanese Patent JPH04352258
Kind Code:
A
Abstract:

PURPOSE: To prevent an asynchronous module from reading and writing wrong data.

CONSTITUTION: The malfunction prevention arbitration system has an asynchronous module request arbitration part 1 which places the asynchronous module in a waiting state for a synchronous module and a forcible acknowledgement generation part 2 which generates forcible acknowledgement with an operation clock break signal and is provided with a synchronous module request premission part 3 which disables the request of the synchronous module when the operation clock is off and a selector 4 which selects the request of the asynchronous module as an arbitration completion signal when the operation clock break signal is inputted, thereby enabling the asynchronous module to read and write normal data even when the operation clock is off.


Inventors:
WAKAYOSHI MITSUHARU
Application Number:
JP12727491A
Publication Date:
December 07, 1992
Filing Date:
May 30, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/16; G06F15/16; G06F15/177; (IPC1-7): G06F12/16; G06F15/16
Attorney, Agent or Firm:
Sadaichi Igita