Title:
MANAGEMENT OF CASH MEMORY RELATED TO SINGLE BUS MULTI-PROCESSOR ARCHITECTURE AND DATA PROCESSING SYSTEM OPERATED BY THE SAME
Document Type and Number:
Japanese Patent JPS63173147
Kind Code:
A
Abstract:
The system consists of multiprocessors P1 to Pn connected to a central memory (9) by means of a single bus (8). Each processor comprises a central-processing unit (1) and a cache memory (2,4). The method consists in dividing the cache memory into two levels (2,4), in causing the write operations issued by the central-processing unit of each processor to be performed in the two cache-memory levels by virtue of a procedure for immediate writing in order to keep, in the second level (4), an updated copy of the information contained in the first level (2), and in updating the corresponding information in the central memory (1) from the second cache-memory level (4) by a procedure for delayed writing. Application: information-processing systems.
Inventors:
MISHIERU SEKUREOBU
TEIERI FURURI
KURISUTEIAN ENTSU
FUIRITSUPU MECHIYU
TEIERI FURURI
KURISUTEIAN ENTSU
FUIRITSUPU MECHIYU
Application Number:
JP33674987A
Publication Date:
July 16, 1988
Filing Date:
December 29, 1987
Export Citation:
Assignee:
THOMSON CSF
International Classes:
G06F12/08; G06F12/0811; (IPC1-7): G06F12/08
Attorney, Agent or Firm:
Yoshio Kawaguchi (2 outside)