MANUFACTURE FOR BIPOLAR TRANSISTOR

Japanese Patent JP3518471

B2

PROBLEM TO BE SOLVED: To reduce resistance of a base-emitter junction by a method, wherein a silicon nitride, and next a silicon oxide are deposited and etched, and these layers are anisotropically etched and cleaned, and a silicon oxide layer is re- etched.
SOLUTION: A thermal oxide 16 is grown on the surface of a substrate 11 as the bottom part of a window W, and on the side face exposed of a polysilicon layer 13. Next, a base region 17 is formed by injection through the thin oxide 16. Next, a silicon nitride layer 18 is equiangularly deposited, next a spacer is formed, and therefore a silicon oxide layer 19 of, for example a thickness of about 150 nm is equiangularly deposited. Next, the oxide layer 19 is anisotropically etched, and the spacer is left behind, and thereafter the nitride layer 18 and the thermal oxide layer 16 are anisotropically etched. Next, cleaning is preferably performed at three stages, and the spacer formed by the layer 19 on a wall of the window W is partially re-etched. As a result, a flare-type profile can be obtained.

Gris, Yvon
Troillard, Germaine

JP2000068526A

April 12, 2004

March 13, 2000

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Stmicroelectronics SA.

H01L29/417; H01L21/225; H01L21/265; H01L21/331; H01L29/73; H01L29/732; (IPC1-7): H01L21/331; H01L29/417; H01L29/732

山本 恵一

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