Title:
MANUFACTURE OF DIODE GATE AND SELF-ALIGNING CONTACT WINDOW
Document Type and Number:
Japanese Patent JPS61176152
Kind Code:
A
Abstract:
A method is provided for obtaining a diode whose contact tapping is self aligned with a gate, consisting in depositing on a semiconductor substrate at least a first layer of a dielectric material, depositing on the last dielectric layer a first layer of polycrystalline silicon so as to form the gate, then a second polycrystalline silicon layer above the first layer, etching in the polycrystalline silicon layers the position of the contact diode until the dielectric layer is laid bare, oxidizing the second polycrystalline silicon layer sufficiently for the oxidized layer to completely cover the first polycrystalline silicon layer forming the gate and only to partially cover the part of the dielectric layer laid bare, and doping the portion of the substrate not covered by the oxide layer so as to form the junction of the diode.
Inventors:
PIEERU BURANSHIYAARU
Application Number:
JP1181186A
Publication Date:
August 07, 1986
Filing Date:
January 22, 1986
Export Citation:
Assignee:
THOMSON CSF
International Classes:
H01L27/146; H01L21/033; H01L21/321; H01L21/768; H01L27/148; (IPC1-7): H01L27/14
Attorney, Agent or Firm:
Yoshio Kawaguchi