Title:
MANUFACTURE OF DRAM CELL
Document Type and Number:
Japanese Patent JP2591927
Kind Code:
B2
Abstract:
PURPOSE: To increase the number of basic chips in the same area by performing only LDD ion-implantation into a DRAM cell of novel structure while omitting heavily doped ion-implantation.
CONSTITUTION: After the first gate oxide film 3, a gate electrode, and a word line polysilicon are deposited without delay, an impurity-implantation process is performed with polysilicon, and using a gate electrode and word line mask, a polysilicon is etched to a predetermined size to form the first gate electrode 4 and a word line 4' pattern. Then, such relatively lightly doped impurity ion- implantation is performed to form the first spacer oxide film 5, and then, such relatively heavily doped impurity ion-implantation is performed to form a substrate MOSFET comprising active regions 6 and 6' of LDD structure. By performing only LDD ion-implantation while omitting heavily doped ion- implantation,a leakage current and punch-through reduction between active regions are minimized, thus the number of basic chips in the same area is increased.
Inventors:
YANAGI YOSHIFUMI
Application Number:
JP3795A
Publication Date:
March 19, 1997
Filing Date:
January 04, 1995
Export Citation:
Assignee:
GENDAI DENSHI SANGYO KK
International Classes:
H01L27/10; H01L21/822; H01L21/8242; H01L27/108; H01L29/786; (IPC1-7): H01L27/108; H01L21/8242; H01L29/786
Domestic Patent References:
| JP62211946A | ||||
| JP6370557A |
Attorney, Agent or Firm:
Akihide Sugimura (8 outside)