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Title:
MANUFACTURE OF ELECTRON SOURCE, IMAGE FORMING DEVICE AND WIRING BOARD, AND ELECTRON SOURCE, IMAGE FORMING DEVICE AND WIRING BOARD USING THE MANUFACTURE
Document Type and Number:
Japanese Patent JP2000311600
Kind Code:
A
Abstract:

To prevent a short-circuiting failure between upper and lower wiring by suppressing continuous growth of a pinhole, by disposing an insulating material on first wiring and forming second wiring on an insulating layer having not less than the specific numbers of layers baked at a specific temperature.

An insulating material No.N is baked at a lower temperature than a softening of an insulating layer No.N (2≤N≤M-1), and a baking temperature for an insulating layer from No.N+1 to No.M (M≥3) is made not more than the baking temperature for the insulating layer No.N. Many element electrodes 1, 2 are arranged and formed on a board 9, and wiring 4 in the X direction is formed by connecting it to an element electrode 2. A first insulating material is applied in the Y direction perpendicular to the wiring 4 in the X direction, and a first layer insulation layer 51 is formed. A second layer insulation layer 52 is formed on the first layer insulation layer 51 at a specific baking temperature, and a third layer insulation layer 53 is formed on the second layer insulation layer 52. Wiring 6 in the Y direction provided with connecting wiring 7 is formed on the third layer insulation layer 53. A conductive film 3 is formed so as to connect the element electrode 1 and the element electrode 2.


Inventors:
YAMADA NOBUTSUGU
Application Number:
JP33121499A
Publication Date:
November 07, 2000
Filing Date:
November 22, 1999
Export Citation:
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Assignee:
CANON KK
International Classes:
H01J1/316; H01J9/02; H01J29/02; H01J29/04; H01J31/12; H05K3/46; H05K1/00; (IPC1-7): H01J9/02; H01J1/316; H01J29/04; H01J31/12; H05K3/46
Attorney, Agent or Firm:
Keisuke Watanabe (1 person outside)