PURPOSE: To reduce the region for surface depletion layer minimizing the parasitic resistance such as source resistance, drain resistance etc. by a method wherein N+ type ion implantation, a source electrode and a drain electrode are self-matched using a tapered insulating film as a mask.

CONSTITUTION: An N type region 5 to be an active layer is formed on a semiinsulating substrate 1 by means of implanting ion such as Si etc. at the dose corresponding to the specified threshold value voltage of MESFET using a photoresist 3 as a mask. An insulating film 11 is etched to be tapered using another photoresist 12 as a mask. Furthermore an N+ type region 4 is formed by means of implanting ion at higher dose. The insulating film 11 on the element forming part is partly etched using a photoresist mask 13 to expose an N+ type region 4. AuGe/Ni etc. are vacuum evaporated to form a source electrode 7 and a drain electrode 8 while the resist 13 is removed and lifted off and then annealed at an optimum temperature to come into ohmic contact. Next another resist 15 is removed to form a photoresist on the insulating film 15 then a metal is formed and the photoresist is removed by means of lift off process to form a gate electrode 9.