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Title:
MANUFACTURE OF HIGH WITHSTAND VOLTAGE SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPH0745526
Kind Code:
A
Abstract:

PURPOSE: To form a complete crystal surface layer part on the surface of a semiconductor wafer, and reduce deterioration of withstand voltage, by planishing the surface of a semiconductor wafer to form a mirror wafer, and growing crystal of the same material as the semiconductor wafer on the surface or implanting elements of the same material.

CONSTITUTION: A semiconductor wafer is cut out from a columnar silicon ingot. If necessary, the surface is cleaned by beveling and etching, and then the wafer surface is planished. After mirror finish is completed, an Si epitaxial layer E which is the same material as the semiconductor wafer W is formed on the surface of the semiconductor wafer W. By forming the epitaxial layer E on the surface of the semiconductor wafer W in this manner, a complete crystal surface layer part F of high completeness is formed on the surface of the semiconductor wafer W.


Inventors:
NAGANUMA TAKASHI
SUGINO YUSHI
YAMADA EIICHI
KITANO MANABU
Application Number:
JP18947493A
Publication Date:
February 14, 1995
Filing Date:
July 30, 1993
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/205; (IPC1-7): H01L21/205
Attorney, Agent or Firm:
Yamato Tsutsui