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Patent Searching and Data


Title:
MANUFACTURE OF LEADLESS IC PACKAGE
Document Type and Number:
Japanese Patent JPS562656
Kind Code:
A
Abstract:

PURPOSE: To obtain efficiently small-sized IC leading package by a method wherein plural IC chips are fitted up on a distributing plate having through holes and the plate is divided finally into small pieces.

CONSTITUTION: Silver pastes 4a, 4b... are applied on conductor patterns having the large areas at the center of conductor patterns 2a, 2b... on a distributing plate having through holes 3a, 3b. IC chips 5a, 5b... are put on them and are heated to be hardened. The IC chips and the distributing plate are connected, covered selectively with Si resins 6a, 6b... and are heated to be hardned. Then the plate is cut along the center part of through holes to divide into small pieces, and packages 7 having external connecting terminals 2a at side faces are completed. As the packages have substrates made of plastic plates, the disconnection due to the difference of thermal expansion coefficient does not take place, and highly reliable circuits can be mass-produced.


Inventors:
NAKAMURA HISASHI
HORIO YASUHIKO
Application Number:
JP7851179A
Publication Date:
January 12, 1981
Filing Date:
June 20, 1979
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L23/12; H01L23/057; H01L23/28; (IPC1-7): H01L23/12; H01L23/30