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Title:
MANUFACTURE OF MIS DIODE
Document Type and Number:
Japanese Patent JPH05152586
Kind Code:
A
Abstract:

PURPOSE: To simplify a manufacturing process by forming a first silicon oxide layer, a polysilicon layer and a second silicon layer on the front surface of a silicon substrate.

CONSTITUTION: A first silicon oxide layer 12 to become 5 gate insulating film is formed on the main surface of a silicon substrate 11 by a thermooxidation method, a first polysilicon layer 13 to become a gate electrode and a second polysilicon layer 14 excepting the gate electrode are formed on this first silicon oxide layer 12 by the same process. Next, a second silicon oxide layer (field insulating layer) 15 thicker than tone first silicon oxide layer 12 is formed by a wet oxidation method in a region where the first and second polysilicon layers 15, 14 are not formed on the surface of the silicon layer 11. Thereby, a manufacturing process can be simplified.


Inventors:
KANAZAWA YURI
Application Number:
JP31064791A
Publication Date:
June 18, 1993
Filing Date:
November 26, 1991
Export Citation:
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Assignee:
SEIKOSHA KK
NIPPON PRECISION CIRCUITS
International Classes:
H01L29/94; (IPC1-7): H01L29/94
Attorney, Agent or Firm:
Kazuko Matsuda



 
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