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Patent Searching and Data


Title:
MANUFACTURE OF MOS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6417475
Kind Code:
A
Abstract:

PURPOSE: To form a lower gate electrode which is not overlapped with the source and drain between insulating regions by forming the insulating regions with an upper gate electrodes as a mask on the surface of a substrate in a double-side gate type MOSFET.

CONSTITUTION: A lower gate insulating film 2, a source region 9, a drain layer 10, a channel layer 11, an upper insulating film 4 and an upper gate electrode 5 are formed on a substrate 1. Then, with the electrode 5 as a mask a semiconductor high resistance substance is doped on the substrate 1 to form an insulator region 7 on the substrate 1. A lower gate electrode 8 which is completely aligned to the electrode 5 is formed between the insulator regions. When it is constructed in this manner, the overlapping capacities of the electrode 8, the regions 9, 10 can be reduced.


Inventors:
HAYASHI HISAO
Application Number:
JP17352987A
Publication Date:
January 20, 1989
Filing Date:
July 11, 1987
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L27/12; H01L29/78; H01L29/786; (IPC1-7): H01L27/12; H01L29/78
Attorney, Agent or Firm:
Hideaki Ogawa