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Title:
MANUFACTURE OF MOS TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5783059
Kind Code:
A
Abstract:

PURPOSE: To form the element of buried gate structure for the subject semiconductor device by a method wherein a semiconductor layer is provided on the substrate, on which a reverse conductive layer was formed on the surface, through the intermediary of an insulating film, and two kinds of ion implanting processes are performed using a channel region as a mask.

CONSTITUTION: An oxide film 2 is provided on a P type substrate 1, and after an N+ layer 3 has been implanted on the above, a P type polycrystalline Si layer 4 is laminated. Then, a resist mask 5 is provided in an expected channel region, a high density of oxygen, for example, is ion-implanted in the N+ layer 3, and subsequently As, for example, is ion-implanted in the polycrystalline Si layer 4. Then, the mask 5 is removed, a heat-treatment is performed, a gate electrode 7 is formed by turning the oxygen implanted section into an SiO2 film, and at the same time, the As implanted section is activated to an N+ type. Subsequently, a patterning is performed on the polycrystalline Si layer, and a self- matched channel region 8 is laid out on the source and drain regions 9 and 10 and the gate electrode 7. Through procedures, a buried gate structure can be formed microscopically.


Inventors:
MIZUTANI YOSHIHISA
Application Number:
JP15854880A
Publication Date:
May 24, 1982
Filing Date:
November 11, 1980
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/02; H01L21/336; H01L27/12; H01L29/78; H01L29/786; (IPC1-7): H01L29/06



 
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