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Title:
MANUFACTURE OF MULTILAYER INTERCONNECTION BOARD
Document Type and Number:
Japanese Patent JPS63141710
Kind Code:
A
Abstract:

PURPOSE: To enable the prevention of void and the improvement of demension accuracy to be achieved by a method in which in molding process, pressure reducing is stopped and the pressure is restored to normal pressure atmosphere, and after prescribed curing time has passed, while continuing heating, pressurizing is quickly released.

CONSTITUTION: One or two inner layer plates in which wiring pattern is formed respectively on both surfaces and the outer layer plate lined with copper, are laminated with the prepreg intervening therebetween. These members are molded in one body, heating and pressurizing them in the atmosphere of reduced pressure. The degree of pressure reduced (vacuum degree) at molding is caused to be 0W10torr in maximum, and in the interval until 30min pass after molding pressure has been applied and the inner temperature of a multilayer interconnection board reaches maximum temperature (170W180°C), the reducing of the pressure is preferably released and restored to normal pressure. At molding, as the molding pressure applied to the multilayer interconnection board, the medium pressure of 25W40kg/cm2 is used. Further, after the passage of prescribed curing time, molding pressure is released, thereby eliminating perfectly voids from the inside of layer or between layers, and suppressing unnecessary resin flow. The multilayer interconnection board with a uniform inner structure is obtained.


Inventors:
OKUBO KAZUO
Application Number:
JP28822886A
Publication Date:
June 14, 1988
Filing Date:
December 03, 1986
Export Citation:
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Assignee:
TOSHIBA CHEM CORP
International Classes:
B29C43/20; B29C43/56; H05K3/46; B29K105/06; B29L31/34; (IPC1-7): B29C43/20; B29C43/56; B29K105/06; B29L31/34; H05K3/46
Attorney, Agent or Firm:
Saichi Suyama



 
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