MANUFACTURE OF OPTICAL INTEGRATED CIRCUIT - NIPPON TELEGRAPH & TELEPHONE

Title:

MANUFACTURE OF OPTICAL INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JPH0212109

Kind Code:

A

Abstract:

PURPOSE:To enable highly-accurate chip segmenting which is superior in mass- productivity and yield by forming a cleavage flaw at a specific position of a wafer peripheral part by laser beam irradiation, then straining the entire surface of the wafer and advancing the cleavage at a time, and segmenting many circuit chips at the same time. CONSTITUTION:A wafer 41 is installed on a stage 49 with a fine adjusting mechanism and the specific position on the wafer periphery is irradiated with a laser beam 43 to specific length to make a flaw 44. Then the wafer 41 is detached from the stage 49 and sandwiched between two transparent cohesive films 54, whose peripheral parts are fixed hermetically to the opening part 56 of a box 55. Then air is admitted to the box 55 from an air intake 57 to increase the internal air pressure and then the films 54 expand owing to the air pressure difference to cleave along the flaw 53 at a time, thereby dividing chips 52 of individual circuits. Consequently, the highly-accurate chip segmenting which is superior in mass-productivity and yield is enabled.

More Like This:

JPH0572432	SINGLE MODE SPACE INTEGRATED OPTICAL FILTER AND ITS IMPLEMENTATION METHOD
JP3009986	PROBLEM TO BE SOLVED: To manufacture a tapered waveguide
JP2010276639	ARRAYED WAVEGUIDE GRATING

Inventors:

NAGAOKA SHINJI
NISHI NORIO
SUZUKI SENTA

Application Number:

JP16091488A

Publication Date:

January 17, 1990

Filing Date:

June 30, 1988

Export Citation:

Click for automatic bibliography generation Help

Assignee:

NIPPON TELEGRAPH & TELEPHONE

International Classes:

G02B6/13; G02B6/12; G02F1/025; H01L21/76; (IPC1-7): G02B6/12; G02F1/025; H01L21/76

Attorney, Agent or Firm:

Hidetoshi Mitsuishi (1 person outside)

Next Patent: JPH0212110