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Patent Searching and Data


Title:
MANUFACTURE OF POWER TRANSISTOR
Document Type and Number:
Japanese Patent JPH02284430
Kind Code:
A
Abstract:

PURPOSE: To lessen the amount of solder used by forming dicing lines so that each region which is surrounded with the dicing lines is not formed on the face of each collector of a semiconductor wafer.

CONSTITUTION: N-type regions 6 and 7 that are formed as respective collectors of each element, P-type region 8 that is formed as a base thereof, and N-type regions 9 that are formed as emitters thereof are formed on a wafer 1 and then solder 5 is applied to the above regions so as to form respective collector electrodes. As only each vertical and horizontal line of dicing lines 2 and 3 are formed on the wafer 1, solder 5 is just applied to the proper thickness of solder and the surplus of it is not left on the wafer. Dicing is performed by positioning the semiconductor wafer with the lines 2 and 3 from the collector electrode sides. Then dicing grooves 10 are formed and further, its wafer is divided into pellets 4 by etching. As each region which is surrounded with the dicing lines is not formed in this way, the amount of solder used is decreased without leaving excessive solder on the respective collector faces.


Inventors:
MOMOI TORU
Application Number:
JP10444789A
Publication Date:
November 21, 1990
Filing Date:
April 26, 1989
Export Citation:
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Assignee:
HITACHI LTD
HITACHI TOBU SEMICONDUCTOR LTD
International Classes:
H01L29/73; H01L21/301; H01L21/331; H01L21/78; H01L29/06; (IPC1-7): H01L21/331; H01L21/78; H01L29/06; H01L29/73
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)