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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH04111325
Kind Code:
A
Abstract:

PURPOSE: To form a short gate length of an FET by forming a window opening of a predetermined diameter in a position where a gate of a semiconductor substrate coated with photoresists of two layers having different sensitivities is formed, and forming a gate of a predetermined length on the substrate by using a metal mask in the window opening formed by obliquely depositing the metal from above the photoresist.

CONSTITUTION: A low sensitivity photoresist 5b and a high sensitivity photoresist 5c are build up on a substrate 1 through an insulating film 4. A window opening 5d of a predetermined diameter is formed in a position where a gate of the substrate 1 is formed, and a lift-off step 5e is further formed near the opening 5d of the upper photoresist 5c. Then, a mask metal is deposited obliquely in direction A from above the photoresist 5c, and the continuous surface from one side inner wall 5d1 to become a deposited surface in the opening 5d to a predetermined position P on the film 4 is covered with a metal mask 7. Thereafter, after the film 4 in the opening 5d is opened, a gate metal 6 is deposited, and a gate G0 of a predetermined length L0 is formed in a predetermined position on the substrate 1.


Inventors:
MORI TOSHIKI
Application Number:
JP23000790A
Publication Date:
April 13, 1992
Filing Date:
August 30, 1990
Export Citation:
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Assignee:
KANSAI NIPPON ELECTRIC
International Classes:
H01L21/302; H01L21/28; H01L21/3065; H01L21/338; H01L29/812; (IPC1-7): H01L21/28; H01L21/302; H01L21/338; H01L29/812
Attorney, Agent or Firm:
Shogo Ehara



 
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