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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0499037
Kind Code:
A
Abstract:

PURPOSE: To form the transistor in the structure having the boundary between source.drain diffused resistor and a substrate in a gentle distribution of concentration in excellent reproducibility by a method wherein, after the removal of a gate electrode sidewall, the whole body is high temperature heat-treated to activate implanted impurities in the state of a substrate surface covered with an outer diffusion preventive insulating film of the impurities in even thickness.

CONSTITUTION: A channeling preventive CVD-SiO2 film 9 and an SiO2 film sidewall 8 are removed by wet-etching step using, e.g. fluoric acid solution. Next, after the formation of an outer diffusin preventive CVD-SiO2 film 12 on the whole surface of this substrate, the whole body is high temperature annealed in an inert gas atmosphere to activate P+ in low concentration P+ implanted region 107 and As+ in high concentration As- implanted region 110 so that n- type low concentration offset regions 7S, 7D and an n+ type high concentration source region 10S, an n+ type high concentration drain region 10D may be formed. Through these procedures, a short channel MOS transistor having the boundary between the source-drain diffused regions and the substrate beneath 8 gate electrode in a gentle distribution of concentration to relieve the electric field in that part can be formed in excellent reproducibility.


Inventors:
SASAKI TAKAE
KIKUCHI YOSHIO
Application Number:
JP20875290A
Publication Date:
March 31, 1992
Filing Date:
August 06, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/336; H01L21/205; H01L21/265; H01L29/78; (IPC1-7): H01L21/205; H01L21/265; H01L21/336; H01L29/784
Attorney, Agent or Firm:
Teiichi



 
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