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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0945881
Kind Code:
A
Abstract:

To enable a heavily doped layer and a correction impurity layer to be optimized in distribution of impurity concentration.

Phosphorus and arsenic ions are implanted into the primary mirror-surface of a semiconductor element forming substrate 1. A semiconductor support substrate 2 where an oxide film 3 thermally oxidized to serve as an insulating layer is formed is pasted on the substrate 1 making its oxide film 3 confront the primary mirror-surface of the substrate 1. Then, the semiconductor element forming substrate 1 is polished, and phosphorus ions are implanted into the polished surface of the substrate 1. Then, all the substrate 1 and the support substrate 2 are thermally treated, whereby a heavily doped layer is formed on the pasted surface of the substrate 1, and a correction impurity concentration is formed on the other surface. Arsenic ions implanted for the formation of the heavily doped layer are smaller in diffusion coefficient than phosphorus ions implanted into the correction impurity layer, so that arsenic ions are not unnecessarily diffused in a final thermal treatment, or a correction impurity layer is formed by implanting phosphorus ions before pasting, whereby the semiconductor element forming substrate 1 is set uniform in concentration as a whole.


Inventors:
SHIRAI YOSHIFUMI
SUZUMURA MASAHIKO
MAEDA MITSUHIDE
HAYAZAKI YOSHIKI
KISHIDA TAKASHI
TAKANO MASAMICHI
Application Number:
JP19076795A
Publication Date:
February 14, 1997
Filing Date:
July 26, 1995
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H01L27/12; H01L21/02; (IPC1-7): H01L27/12; H01L21/02
Attorney, Agent or Firm:
Ishida Chochichi (2 outside)