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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5910254
Kind Code:
A
Abstract:

PURPOSE: To form an MIS type capacity element on the same semiconductor substrate as an MIS type field effect transistor by a method wherein the semiconductor region of a second conductivity type is formed at a part of the surface of the semiconductor substrate of a first conductivity type, and polycrystalline semiconductor layers are formed via an insulation film.

CONSTITUTION: A P type semiconductor region 4 is formed by diffusing boron from the window 3 of the insulation film 2 on an N type semiconductor substrate 1. A window 6 is formed, and then oxide films 7a and 7b are formed by thermal oxidation method and used as the dielectric of a capacity element and the gate oxide film of a field effect transistor. A P type depletion channel layer 9 is formed by implanting boron, a polycrystalline semiconductor layer is formed and selectively removed, and thus window openings and the polycrystalline semiconductor layers 13, 14 are formed. A P+ layer 15, a P type drain region 16 and a P type source region 17 are formed by diffusing boron. An insulation film 18 is formed and selectively removed, resulting in the formation of electrode lead-out contact holes, and then the lead-out electrodes 19a and 19b of an MIS type capacity element 20a and a drain electrode 19c, source electrode 19d and gate electrode 19e of an MIS type field effect transistor 20b are formed.


Inventors:
MASUDA KENZOU
Application Number:
JP8910283A
Publication Date:
January 19, 1984
Filing Date:
May 23, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/04; H01L21/822; H01L27/06; H01L29/78; (IPC1-7): H01L27/04; H01L29/78
Domestic Patent References:
JPS4832489A1973-04-28
JP43021393A
JPS4985975A1974-08-17
Attorney, Agent or Firm:
Katsuo Ogawa