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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6094777
Kind Code:
A
Abstract:

PURPOSE: To obtain an EEPROM which performs the shortening of time required for writing and erasing by forming a conductive electrode through a thin insulating film on a semiconductor substrate which includes an impurity diffused region which contains a microdefect layer.

CONSTITUTION: An n+ type diffused region 104 which contains a microdefect layer 103 is formed on a region separated by a field oxide film 102 of a p type silicon substrate 101, and a floating gate 107 is formed through an oxide film 106 on the substrate 101 which includes the region 104. When a negative voltage is applied to the gate 107 of the EEPROM cell, a microdefect effectively operates as the recombination center of carrier to shorten the lifetime of minority carrier. Accordingly, the formed depletion layer does not extend over the maximum depletion layer width, but sufficient voltage can be applied to the film 106. Consequently, the implantation and exhaust of charge to the gate 107 can be accelerated to shorten the time required for writing and erasing information.


Inventors:
MIZUTANI YOSHIHISA
Application Number:
JP20312183A
Publication Date:
May 27, 1985
Filing Date:
October 29, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue