Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6243173
Kind Code:
A
Abstract:
PURPOSE: To prevent the expansion of a source region due to diffusion of phosphorus, by coating a gate electrode with photoresist when arsenic is implanted, and coating the source region with photoresist when the phosphorus is implanted.
CONSTITUTION: In order to form a source region 54 and a drain region 51, arsenic As+ is implanted. Since a gate electrode 4 is coated with photoresist 6 at this time, the arsenic is not implanted in the gate electrode 4. Then, a pattern 62 is formed so that only a low-implantation-quantity region 52 is not coated with photoresist. Phosphorus P+ is implanted in the low-implantation- quantity region 52. At this time, since the source region 4 is coated with the photoresist, the phosphorus is not injected.
Inventors:
OBATA MASANORI
Application Number:
JP18160485A
Publication Date:
February 25, 1987
Filing Date:
August 21, 1985
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Saburo Kimura (1 outside)