Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6449255
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of lithographic processes by a method wherein, when a high-concentration impurity layer is to be formed in a source-drain part of an Nch transistor, ions of silicon are implanted into a whole face and the source-drain part into which the ions have been implanted of a Pch is removed.

CONSTITUTION: A MOS gate electrode is formed on an N-type diffusion layer 2 of a main face 1 of a P-type silicon substrate; a lowconcentration impurity layer 4 is formed in source-drain parts of an Nch transistor (hereinafter called 'Nch Tr') ; spacers 5 composed of a silicon dioxide film are formed on side walls on both sides of the MOS gate electrode. Then, ions of silicon are implanted; high-concentration impurity layers 6 are formed in the sourcedrain parts of the Nch Tr; after that, the Nch Tr is covered with a photoresist 7; the source-drain parts 6 into which silicon of a Pch transistor has been implanted are etched. Then, boron is implanted into the source-drain parts of the Pch transistor; thereby forming high-concentration impurity layers 8.


Inventors:
SATOU TOMOWAKA
Application Number:
JP20509387A
Publication Date:
February 23, 1989
Filing Date:
August 20, 1987
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L27/088; H01L21/8234; H01L27/08; H01L27/10; (IPC1-7): H01L27/08; H01L27/10
Attorney, Agent or Firm:
Koji Hoshino