PURPOSE: To reduce a parasitic capacity between electrodes and impurity layers and thereby to obtain a device of high integration by forming first a large first electrode, making an impurity region by using this electrode as a mask, removing later a part of the first electrode, and providing a second electrode in the place from which the part is removed.

CONSTITUTION: One main surface of an Si substrate 5 is covered with a thick oxide film 18, a gate oxide film 19 is formed selectively in a prescribed region, and a poly-Si gate electrode (the first electrode) 13 of a transistor Q3 is provided thereon. The oxide film 19 is etched by using the electrode 13 as a mask, impurity layers 3' and 4' are made thereon, thermal oxidation is applied, and thereby the electrode 13 and the layers 3' and 4' are covered with an oxide film 14. Next, a part of the electrode 13 is removed by etching so as to open the surface 20 of the channel part of the transistor Q3. Then, a gate oxide film 21 is made to grow in an opening part 20 by thermal oxidation, the remaining side surface of the electrode 13 is covered with an oxide film, and an Al gate electrode (the second electrode) 12 is provided. According to this constitution, an impurity laver between the serial connection elements Q2 and Q3 of a three- element memory cell is unnecessitated, and thereby an area occupied therby is reduced, while a parasitic capacity between the electrodes and the impurity layers is also reduced.