MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JPH02337

Kind Code:

A

Abstract:

PURPOSE: To improve the degree of integration by a method wherein impurities are introduced in a semiconductor substrate to stack two buried layers of different conductivity type in the manner of self-alignment.

CONSTITUTION: After a thin SiO2 film 12 and an oxidation-resistant Si3N4 film 13 formed on a P-type Si substrate surface are selectively eliminated, an N-type buried layer 14 is formed by introducing impurity, and a thick SiO2 film 15 is formed by thermal oxidation. After the film 13 is eliminated, a P-type channel stopper 16 is formed. After the films 12, 15 are eliminated, an N- type epitaxial layer 14 and a thin SiO2 film 18 are formed, and further an Si3N4 film 19 is selectively formed. By using the film 19 as a mask and performing heat treatment, a field oxide film 20 is formed to a depth not reaching the N+ type buried layer 14. By selective ion-implantation, a collector connection region 21, a base region 22 and an emitter region 23 are formed.

Inventors:

ISHIKAWA TAKASHI
OGIUE KATSUMI
ODAKA MASANORI
NITTA TAKEHISA

Application Number:

JP31635888A

Publication Date:

January 05, 1990

Filing Date:

December 16, 1988

Export Citation:

Click for automatic bibliography generation Help

Assignee:

HITACHI LTD

International Classes:

H01L29/73; H01L21/331; H01L21/74; H01L21/76; H01L21/761; H01L29/72; H01L29/732; (IPC1-7): H01L21/331; H01L21/74; H01L21/76; H01L29/72; H01L29/73

Domestic Patent References:

JPS558095A	1980-01-21
JPS5559738A	1980-05-06
JPS5643756A	1981-04-22

Attorney, Agent or Firm:

Katsuo Ogawa (1 person outside)

Next Patent: JPH02338