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Title:
MANUFACTURE OF SEMICONDUCTOR MEMORY STORAGE
Document Type and Number:
Japanese Patent JPS60150665
Kind Code:
A
Abstract:

PURPOSE: To determine reference potential capable of stably deciding a memory content at high speed by forming a plurality of capacitors for preparing the reference potential of a sense amplifier section and connecting capacitors only in required number in a plurality of the capacitors in parallel with necessary sections at the same time as the memory content is set by using a photoetching mask.

CONSTITUTION: In a process in which a memory cell section, a sense amplifier section, a digit line G, an address line, etc. are formed to a semiconductor substrate, a plurality of capacitors C11, C12,..., C1i...C1n for preparing the reference potential of the sense amplifier section are shaped. Where C11 takes the optimum value at a time when all memory cells are not connected to the digit line G and ΣC1i the optimum value at a time when all memory cells are connected to the digit line G, and C12, C13...C1n have the capacitance of (ΣC1i-C11d)/ (n-1), equal capacitance. These capacitors determine an ROM content by using a mask for varying the ROM content while connecting only the capacitor having an optimum capacitance value section to a circuit.


Inventors:
KOBAYASHI MASAHIRO
Application Number:
JP661384A
Publication Date:
August 08, 1985
Filing Date:
January 18, 1984
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C17/08; H01L21/8234; H01L27/06; H01L27/10; (IPC1-7): G11C17/00; H01L27/06
Attorney, Agent or Firm:
Uchihara Shin



 
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