Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH05211313
Kind Code:
A
Abstract:

PURPOSE: To thinly form a capacitor insulating film between an earth wiring and a gate electrode in a SRAM memory cell with excellent uniformity.

CONSTITUTION: After an element isolation field oxide film 2, a gate oxide film 2b, and gate electrodes 3a and 3b have been formed on a P-type silicon substrate 1, source and drain 4a, 4b and 4c are formed. Then, a CVD oxide film 5 of 40nm in thickness, which becomes a capacity insulating film, and a polysilicon 6 of 200nm in thickness are deposited. Then, a contact hole 7 is perforated. The thin oxide film, which is grown in the contact hole when photoresist is removed, is etched by dilute hydrofluoric acid. At this time, as the CVD oxide film 5 is covered by polysilicon 6, there is no thinning of film. Polysilicon 6 of 200nm in thickness is deposited on the whole surface again. Then, the polysilicon 6 is patterned, and an earthing wiring 8 is formed.


Inventors:
HORIBA SHINICHI
Application Number:
JP115192A
Publication Date:
August 20, 1993
Filing Date:
January 08, 1992
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H01L27/11; H01L21/8244; (IPC1-7): H01L27/11
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
Previous Patent: JPS5211312

Next Patent: MOS STASTIC MEMORY