PURPOSE: To enable the standardization of chip size and positions of external connection pads by a method wherein the chip size of an IC and the arrangement of I/O cells in the chip periphery are fixed, and logic cells and the memory part are arranged inside the I/O cells by making the arrangement variable.

CONSTITUTION: A boundary 2 is provided in the periphery of a chip 1, and the outside of the boundary is made as the I/O cell region 3, in which region the arrangement of the I/O cells 4 is fixed. The inside of the boundary 2 is the region of free arrangement: a memory 5 is arranged at the corner right below, and its size is made variable. The logic parts are arranged in the remaining region; for example, logic cells 6 are put in the array direction and each array is made variable so as to be moved left and right; thereby, cells come to freely move left and right according to the size of the logic part. Power source lines 7 and 8 are made to run in the array direction and connected to each cell. The solid line indicates the first wiring layer, and the dotted line the second wiring layer. External connection pads 9 are arranged in the chip periphery and wired to the I/O cells 4.