Title:
エピタキシャルウェーハの製造方法
Document Type and Number:
Japanese Patent JP6372709
Kind Code:
B2
Abstract:
The present invention is a method for producing an epitaxial wafer, said method comprising a preparation step and a growth step. In the preparation step, a low resistivity substrate W which has been doped with red phosphorus is prepared. The substrate W has at least 5x1019 atoms/cm3 of phosphorus added as a dopant. In the growth step, an epitaxial layer is grown at a growth rate of 2 μm/min or lower on the substrate W at a temperature between 1040°C and 1130°C inclusive. In this way, the present invention provides a method for producing an epitaxial wafer in which lamination defects can be suppressed.
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Inventors:
Yoshioka Shohei
Application Number:
JP2016084435A
Publication Date:
August 15, 2018
Filing Date:
April 20, 2016
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
H01L21/205; C23C16/24; H01L21/20
Domestic Patent References:
| JP2012156303A | ||||
| JP2015213102A | ||||
| JP2014082242A | ||||
| JP2012114138A |
Foreign References:
| WO2014175120A1 | ||||
| WO2000054893A1 |
Attorney, Agent or Firm:
Ryuji Harikawa