Title:
積層型チップ部品の製造方法
Document Type and Number:
Japanese Patent JP4034483
Kind Code:
B2
Abstract:
A laminated chip component including: alternately laminated conductive patterns (13,43,63) and insulating sheets (11,41,61); through-holes (12,42,62) which are provided in the insulating sheets and connect top layer conductive patterns to bottom layer conductive patterns; auxiliary conductive patterns (15,45,65) which are provided on the top faces of the conductive patterns at positions facing the through-holes provided in adjacent insulating sheets; and conductors (14,64) which are provided in the through-holes. The auxiliary conductive patterns can be substituted by conductor sections (16,66) which are provided in the insulating sheets at the positions facing the through-holes provided in adjacent insulating sheets. And, a method for manufacturing a laminated chip component is also disclosed.
Inventors:
Muramatsu Nobuaki
Takahiro Ogawa
Takahiro Ogawa
Application Number:
JP26985699A
Publication Date:
January 16, 2008
Filing Date:
September 24, 1999
Export Citation:
Assignee:
Toko Co., Ltd.
International Classes:
H01F17/00; H01F41/04; H01G4/40; H03H1/00; H03H7/01; H05K1/11
Domestic Patent References:
| JP1295407A | ||||
| JP2251120A | ||||
| JP5259600A | ||||
| JP7154073A | ||||
| JP818236A | ||||
| JP1140922A |