Title:
積層型キャパシターを備える半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4279443
Kind Code:
B2
Abstract:
Disclosed is a method for fabricating a semiconductor device including stacked capacitors on a semiconductor substrate having a logic circuit region formed with a circuit and a RAM cell region formed with a plurality of transistors, involving the steps of forming an insulating film to a thickness corresponding to a height of stacked capacitors, to be formed, over an upper surface of the semiconductor substrate, partially removing the insulating film from the RAM cell region, thereby forming a space in which the stacked capacitors are to be formed, forming the stacked capacitors in the space, and partially removing the insulating film from the logic circuit region, and forming interconnection lines for the logic circuit in a space defined in the logic circuit region by virtue of the removal of the insulating film. In accordance with this method, steps formed during the formation of capacitors are removed prior to subsequent processing steps for forming layers over those capacitors. Accordingly, it is possible to accurately pattern the layers formed after the formation of the capacitors. It is also possible to achieve a desired fineness of interconnection lines.
Inventors:
Gold
Application Number:
JP2000300787A
Publication Date:
June 17, 2009
Filing Date:
September 29, 2000
Export Citation:
Assignee:
Tobu Electronics Co., Ltd.
International Classes:
H01L21/8242; H01L27/10; H01L21/02; H01L21/70; H01L27/108; H01L21/768
Domestic Patent References:
| JP10079491A | ||||
| JP11026718A | ||||
| JP10289984A | ||||
| JP4012564A |
Foreign References:
| US5895239 |
Attorney, Agent or Firm:
Shuichiro Kitamura