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Patent Searching and Data


Title:
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2008294195
Kind Code:
A
Abstract:

To provide a manufacturing method of a semiconductor device capable of suppressing increase in the contact resistance caused by the shrinkage of a diffusion layer region, even when forming the diffusion layer region thiny.

When forming the diffusion layer region 5 separated by an element isolation region, the diffusion layer region 5 is formed separately in two stages by using a double exposure technique. Thus, even when forming the diffusion layer region 5 thiny, the shrinkage at both ends in the longitudinal direction of the diffusion layer region 5 is suppressed, and the increase of the contact resistance is suppressed, while securing the connection area of both ends in the longitudinal direction of the diffusion layer region 5 and a contact plug 13 embedded in a contact hole 12.


Inventors:
SUGIOKA SHIGERU
Application Number:
JP2007137687A
Publication Date:
December 04, 2008
Filing Date:
May 24, 2007
Export Citation:
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Assignee:
ELPIDA MEMORY INC
International Classes:
H01L21/8242; H01L27/108; H01L29/78; H01L29/786
Attorney, Agent or Firm:
Sumio Tanai
Tadashi Takahashi
Naoki Ofusa
Kazunori Onami