Title:
半導体装置の作製方法
Document Type and Number:
Japanese Patent JP6474625
Kind Code:
B2
Abstract:
To provide a semiconductor device with low parasitic capacitance, a semiconductor device with low power consumption, a semiconductor device having favorable frequency characteristics, or a highly integrated semiconductor device. In a method of manufacturing a semiconductor device including a semiconductor, a first conductor, a second conductor, a third conductor, and an insulator, the semiconductor includes a first region in contact with the first conductor, a second region in contact with the second conductor, and a third region in contact with the insulator. The third conductor includes a region in which the third conductor and the semiconductor overlap with each other with the insulator interposed therebetween. The first region, the second region, and the third region do not overlap with each other. The first conductor is selectively grown over the first region, and the second conductor is selectively grown over the second region.
Inventors:
Tetsuhiro Tanaka
Application Number:
JP2015015863A
Publication Date:
February 27, 2019
Filing Date:
January 29, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; G09F9/00; G09F9/30; H01L21/28; H01L21/8238; H01L21/8239; H01L21/8242; H01L27/088; H01L27/092; H01L27/105; H01L27/108; H01L27/115; H01L27/1156; H01L29/417; H01L29/423; H01L29/49; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP2008112909A | ||||
| JP2015504603A | ||||
| JP6061259A | ||||
| JP2004363636A | ||||
| JP8139337A | ||||
| JP7135318A | ||||
| JP8213494A | ||||
| JP4147629A | ||||
| JP8186265A | ||||
| JP2013048220A | ||||
| JP2011146694A | ||||
| JP2013048217A |
Foreign References:
| WO2013075028A1 | ||||
| US6074900 | ||||
| US6087698 | ||||
| US5341028 | ||||
| US20130020570 | ||||
| US20130023087 |